Karim Sabra

Organization: CNRS – Institut de Physique des 2 Infinis (IP2I), Lyon

Context: 2nd year of apprenticeship (4th year engineering diploma)

What I did

• Migrated PLL from TSMC 130 nm to TowerJazz 180 nm
• Resized transistors and redesigned loop filter
• Ran Spectre simulations (PFD, charge pump, VCO, divider, full loop)
• Validated lock time (1.5–2 µs), jitter (~2 ps RMS), stable 160 MHz output
• Performed layout design: floorplanning, guard rings, parasitic extraction
• Optimized post-layout: frequency 2.58 GHz, jitter reduced to 7 ps

Results

• PLL validated and integrated in PICMIC-1 ASIC
• Stable 160 MHz output clock
• Gained autonomy in analog layout and verification

Deliverables

Full 4th Year Report (FR, PDF)

Context: Academic FPGA project covering metastability, FSM design, and serial communication in VHDL.

What I did

• Metastability study: Implemented flip-flops in VHDL, simulated setup/hold time violations, and validated synchronizers.
• Stepper motor driver: Designed FSMs for multiple drive modes (Full Step Low/High Torque, Half Step Precision) and tested with a on FPGA.
• Clock divider: Built a dynamic divider in VHDL to control motor speed and synchronize FSM modules.
• UART communication: Implemented TX/RX FSMs, baudrate generator, oversampling logic, and validated loopback on FPGA.

Results

• Strengthened skills in digital design, VHDL, and FPGA prototyping.
• Validated FSMs through ModelSim simulations and FPGA hardware tests.
• Improved autonomy in clock domain management and serial interfaces.

Deliverables

Full Report (FR, PDF)

Context: Academic project covering clean-room fabrication, analog circuits, and PCB prototyping

What I did

• Hands-on clean-room training: photolithography, spin-coating, UV exposure, metal deposition
• Designed analog conditioning circuits with op-amps
• Created PCB with KiCad
• Hand-soldered the PCB and assembled full sensor chain
• Tested STM32 drivers (timers OK, ADC partial)

Results

• Complete microsensor workflow from fabrication to validation
• Operational analog front-end, partial digital acquisition
• Practical training in microfabrication + PCB assembly

Deliverables

Poster presentation (FR, PDF)

Organization: Instituto de Microelectrónica de Sevilla (IMSE-CNM, CSIC/US)

Context: International internship – supervised by Dr. José M. de la Rosa

What I did

• Reviewed CT ΣΔ theory (noise shaping, OSR, SNR, SNDR, ENOB)
• Parametric sweeps on Active-RC and Gm–C designs using Spectre/OCEAN
• Developed unified OCEAN automation script
• Built Python GUI (Tkinter) to manage sweeps interactively
• Generated validated datasets (CSV + SNR/SNDR plots) for AI/ML use

Results

• Reusable automation flow across topologies
• Clean datasets for ML training
• Improved handover with documented GUI + reports

Deliverables

Internship Report (EN, PDF)

Context: Side project collaboration to integrate the Vicuna RISC-V vector coprocessor into the X-HEEP microcontroller, targeting FPGA prototyping and benchmarking.

What I’m doing

• Studying X-HEEP architecture, memory banks, bus interfaces, and CLINT/PLIC interrupts.
• Reviewing Vicuna’s coprocessor interface and supported RISC-V instructions.
• Defining the integration path via X-HEEP’s exposed master/slave ports and core-v-x interface on cv32e40x.
• Building a simulation harness, adding smoke tests for vector add, multiply, and AXPY.
• Targeting FPGA bring-up to run kernels and measure cycle counts and throughput.

Status

In progress

Stack

SystemVerilog, Verilator, FuseSoC, Vivado, RISC-V GCC, FreeRTOS

Planned Deliverables

• HDL repository and build scripts
• Integration notes and bring-up guide
• Benchmark results on AXPY, 3×3 convolution, and GEMM
• Short demo video

Why it matters

X-HEEP is a configurable open-source RISC-V microcontroller designed to attach external accelerators and peripherals. Vicuna is a timing-predictable vector coprocessor that ensures repeatable execution and no timing anomalies, making it valuable for worst-case execution time analysis while still accelerating data-parallel workloads.